library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity xie is
	port (
		request : in std_logic;
		sel    : out std_logic_vector(1 downto 0);
		wrreq0 : out std_logic;
		wrreq1 : out std_logic;
		wrreq2 : out std_logic;
		wrreq3 : out std_logic);
end xie;

architecture RTL of xie is
	signal count: std_logic_vector(1 downto 0);
begin
	process(request)
	begin
		if (request'event and request='1') then
			count <= count + 1;
		end if;
		if (request='0') then
			wrreq0 <= '0';
			wrreq1 <= '0';
			wrreq2 <= '0';
			wrreq3 <= '0';
		end if;
		if (count="00") then			
			sel <= count;
			wrreq0 <= '1';
			wrreq1 <= '0';
			wrreq2 <= '0';
			wrreq3 <= '0';
		elsif (count="01") then
			sel <= count;
			wrreq0 <= '0';
			wrreq1 <= '1';
			wrreq2 <= '0';
			wrreq3 <= '0';
		elsif (count="10") then
			sel <= count;
			wrreq0 <= '0';
			wrreq1 <= '0';
			wrreq2 <= '1';
			wrreq3 <= '0';
		elsif (count="11") then
			sel <= count;
			wrreq0 <= '0';
			wrreq1 <= '0';
			wrreq2 <= '0';
			wrreq3 <= '1';
		end if;
 	end process;
end RTL;